Building your eFPGA

This contains a guide and information on building your custom eFPGA.

• Fabric definition
  • Current Fabric Limitations
  • Fabric CSV description
  • Fabric layout
  • Tiles
  • Tile CSV description
    • Wires
    • Switch matrix
    • Primitives
      • VHDL attribute syntax
      • BelMap Attribute
        • Verilog BelMap
        • VHDL BelMap
        • The FAB_ATTR_ prefix
    • Bitstream remapping
  • Supertiles
    • Modelling
    • Supertile Functionality
• Building fabric
  • Create a new project
    • The .FABulous directory
  • Running the FABulous shell
  • Load the fabric CSV definition file
  • Generate switch matrix
  • Generate the configuration storage (RTL)
  • Generate the actual tiles (RTL)
  • Generate the entire fabric (RTL)
  • Generate Verilog top wrapper
  • Generate the nextpnr model
  • Generate the metadata list for FASM → Bitstream
• FABulous Fabric Automation
  • Generating Custom Tiles
    • Generating and testing a custom tile
      • Preparation
      • Annotating the BEL
      • Tile Config Generation
      • Tile CSV Generation
      • Switch Matrix Generation
      • CAD Tool Integration
      • Generating the Fabric
      • Testing the Tile
    • Working with multiple BELs
      • Shared RESET and ENABLE Ports
      • Carry Chains
      • Annotating the BELs
      • Generating the Custom Tile
  • Generative IOs (GEN_IO)
    • GEN_IO Parameters
    • GEN_IO Example
• Convert your design into GDSII format
  • Prerequisites
    • Install tools
    • Enter the Nix environment
    • Install PDK
  • Changing PDK
  • Tile to GDS
    • Command Options
    • Tile Config
    • Pin Config
  • Stitching the tiles
  • Full Automated Flow
    • When to use the automated flow
    • Working with pre-hardened macros
  • Tile Size Optimisation
    • Optimisation Modes
    • How Optimisation Works
    • Related Variables
  • Output Structure
    • Key Metrics
    • Viewing Results
  • Troubleshooting
• Timing Characterization
  • How it works (high level)
  • Running the timing model from the CLI
    • Examples
  • Configuration JSON: fields and meaning
    • Example configuration (shortened)
  • Using templates and per-tile overrides
  • Outputs
  • Debugging and common issues
  • Programmatic usage
• GDS Flow Configuration Variables
  • Add Buffers
  • Auto Eco Diode Insertion
  • Conditional Magic DRC
  • Detailed Routing Timed
  • Diodes On Ports
  • Extract PDK Info
  • Fabric Area Optimisation
  • Fabric IO Placement
  • Fabric Macro Flow
  • Fabric Optimisation Flow
  • Generate PDN
  • Magic Stream Out
  • PDN
  • Round Die Area
  • Tile Area Optimisation
  • Tile IO Placement
  • Tile VHDLMacro Flow Classic
  • Tile Verilog Macro Flow